1. Field of the Invention
This invention relates to semiconductor integrated circuit (IC) devices, and more particularly, to a method of fabricating a metal-oxide semiconductor (MOS) transistor with reduced level of degradation caused by hot carriers.
2. Description of Related Art
In designing MOS transistors, if the channel between the source/drain regions is reduced in size, the depletion regions in the source/drain regions will be overlapped with the channel, which effectively further reduces the size of the channel. In an enhancement mode MOS transistor, for example, if the bias applied thereto is fixed, the foregoing effect will cause the transversal electric field across the channel to be increased. As a consequence of this, the electrons in the channel will gain energy from the increased electric field. Therefore, the electrons near the junction between the channel and the drain region will be higher in energy than the electrons elsewhere that are in thermal equilibrium. These electrons are thus customarily referred to as "hot electrons". In proton-type MOS transistors, the energized protons are called "hot protons". Generically, these two kinds of carriers are both referred to as "hot carriers".
Since the hot carriers near the drain region gain an energy higher than the energy gap in the MOS transistor, the covalent electrons near the drain regions will be hit by these hot carriers and thereby raise in energy level to the conduction band. As a result, more electron-hole pairs will be produced. In conclusion, if the channel in the MOS transistor is shortened, the number of carriers in the channel near the drain region will be increased. This phenomenon is customarily referred to as "carrier multiplication".
These electrons that are additionally produced due to carrier multiplication will be attracted to the drain region, thus increasing the current in the drain region. In addition, part of these electrons can penetrate into the gate dielectric layer, thus causing the generation of more holes.
One part of these holes will flow to the substrate, thus causing a current flow in the substrate; and the other part of the same will be captured by the source region, thus causing an enhancement to the NPN junction that will cause the generation of more hot electrons. This increased level of carrier multiplication will cause the adverse effect of electrical breakdown in the MOS transistor, which means a degradation to the performance and characteristics of the MOS transistor.
One solution to reduce the level of carrier multiplication is to form a lightly doped diffusion (LDD) region in the source/drain regions near the channel, which is doped with a less concentration of impurities than the source/drain regions so as to reduce the intensity of the electric field across the channel. A conventional method for forming an LDD region in a MOS transistor is described in the following with reference to FIGS. 1A through 1C.
Referring first to FIG. 1A, in the foremost step, a semiconductor substrate, such as a silicon substrate 10, is prepared. The silicon substrate 10 is then subjected to local oxidation of silicon (LOCOS) so as to form at least a pair of field oxide layers 12 thereon, which defines an active region on the silicon substrate 10. Thereafter, a gate dielectric layer 14 and a polysilicon gate layer 16 are successively formed over the active region, which two layers in combination form a gate (14, 16) for the MOS transistor.
Referring further to FIG. 1B, in the subsequent step, a pair of LDD regions 18 is formed on the silicon substrate 10 by diffusing an impurity semiconductor with a low concentration into the regions on either side of the gate (14, 16).
Referring finally to FIG. 1C, in the subsequent step, a layer of a dielectric material, such as silicon dioxide, is formed on the sidewall of the gate (14, 16), which serves as a spacer 19 for the gate (14, 16). Thereafter, a pair of source/drain regions 20 are formed on the silicon substrate 10 by doping the same type of impurity semiconductor with a high concentration (i.e., the same impurity semiconductor that is used earlier to form the LDD regions 18 but here is applied with a higher concentration) into the LDD regions 18. At the same time during this process, the polysilicon gate layer 16 is also doped, such that the conductivity thereof is increased.
One major drawback to the foregoing method, however, is that the gate dielectric layer 14 could be easily get damaged during the process of doping the impurity semiconductor into the wafer to form the heavily doped regions that serve as the source/drain regions. Moreover, although the provision of the LDD regions in the source/drain regions can reduce the hot carrier effect, there are still a small number of hot carriers that will be accelerated by the electric field across the channel, which causes a high current in the channel that will then cause an electrical breakdown in the MOS transistor. Some of these hot carriers will even cross the gate dielectric layer 14 to the polysilicon gate layer 16 and thereby be trapped in the gate dielectric layer 14. The trapped carriers will cause a change in the amount of electric charges in the gate dielectric layer 14, thus altering the threshold voltage (V.sub.t) of the MOS transistor. The characteristics and performance of the MOS transistor thus could be degraded.